#ifndef _REGS_H
#define _REGS_H
/*
  author Sylvain Bertrand <digital.ragnarok@gmail.com>
  Protected by GNU Affero GPL v3 with some exceptions.
  See README at root of alga tree.
*/

/*
 * many masks are 0xfffffff because we need the info from AMD
 * or need to deduce from other values in the register
 */

#define SET(n, x) (((x) << n##_SHIFT) & n##_MASK)
#define GET(n, x) (((x) & n##_MASK) >> n##_SHIFT)

#define	VGA_RENDER_CTL				0x300
#define		VGA_VSTATUS_CTL_MASK			0x00030000
#define		VGA_VSTATUS_CTL_CLR			0xfffcffff

#define VGA_MEM_BASE_ADDR			0x310
#define VGA_MEM_BASE_ADDR_HIGH			0x324

#define	VGA_HDP_CTL				0x328
#define		VGA_MEM_PAGE_SELECT_EN			BIT(0)
#define		VGA_MEM_DIS				BIT(4)
#define		VGA_RBBM_LOCK_DIS			BIT(8)
#define		VGA_SOFT_RESET				BIT(16)

#define	D0VGA_CTL				0x330
#define		DVGA_CTL_MODE_ENA			BIT(0)
#define		DVGA_CTL_TIMING_SELECT			BIT(8)
#define		DVGA_CTL_SYNC_POLARITY_SELECT		BIT(9)
#define		DVGA_CTL_OVERSCAN_TIMING_SELECT		BIT(10)
#define		DVGA_CTL_OVERSCAN_COLOR_ENA		BIT(16)
#define		DVGA_CTL_ROTATE				BIT(24)
#define D1VGA_CTL				0x338
#define D2VGA_CTL                         	0x3e0
#define D3VGA_CTL                         	0x3e4
#define D4VGA_CTL                         	0x3e8
#define D5VGA_CTL                         	0x3ec

#define DMIF_ADDR_CFG				0xbd4

/*----------------------------------------------------------------------------*/
#define HPD0_INT_STATUS				0x601c
#define HPD0_INT_CTL				0x6020
#define HPD0_CTL				0x6024

#define HPD1_INT_STATUS				0x6028
#define HPD1_INT_CTL				0x602c
#define HPD1_CTL				0x6030

#define HPD2_INT_STATUS				0x6034
#define HPD2_INT_CTL				0x6038
#define HPD2_CTL				0x603c

#define HPD3_INT_STATUS				0x6040
#define HPD3_INT_CTL				0x6044
#define HPD3_CTL				0x6048

#define HPD4_INT_STATUS				0x604c
#define HPD4_INT_CTL				0x6050
#define HPD4_CTL				0x6054

#define HPD5_INT_STATUS				0x6058
#define HPD5_INT_CTL				0x605c
#define HPD5_CTL				0x6060

#define		HPDx_INT_STATUS				BIT(0)
#define		HPDx_INT_STATUS_SENSE			BIT(1)
#define		HPDx_INT_STATUS_RX			BIT(8)

#define		HPDx_INT_CTL_INT_ACK			BIT(0)
#define		HPDx_INT_CTL_INT_POLARITY		BIT(8)
#define		HPDx_INT_CTL_INT_ENA			BIT(16)
#define		HPDx_INT_CTL_RX_INT_ACK			BIT(20)
#define		HPDx_INT_CTL_RX_INT_ENA			BIT(24)

/* timers are micro seconds */
#define		HPDx_CTL_CONN_TIMER_MASK		0xffffffff
#define		HPDx_CTL_CONN_TIMER_SHIFT		0
#define		HPDx_CTL_RX_INT_TIMER_MASK		0xffffffff
#define		HPDx_CTL_RX_INT_TIMER_SHIFT		16
#define		HPDx_CTL_ENA				BIT(28)
/*----------------------------------------------------------------------------*/

#define DISP0_INT_STATUS			0x60f4
#define		LB_D0_VLINE_INT				BIT(2)
#define		LB_D0_VBLANK_INT			BIT(3)
#define		HPD0_INT				BIT(17)
#define		HPD0_RX_INT				BIT(18)
#define		DACA_AUTODETECT_INT			BIT(22)
#define		DACB_AUTODETECT_INT			BIT(23)
#define		I2C_SW_DONE_INT				BIT(24)
#define		I2C_HW_DONE_INT				BIT(25)
#define DISP1_INT_STATUS			0x60f8
#define		LB_D1_VLINE_INT				BIT(2)
#define		LB_D1_VBLANK_INT			BIT(3)
#define		HPD1_INT				BIT(17)
#define		HPD1_RX_INT				BIT(18)
#define		DISP_TIMER_INT				BIT(24)
#define DISP2_INT_STATUS			0x60fc
#define		LB_D2_VLINE_INT				BIT(2)
#define		LB_D2_VBLANK_INT			BIT(3)
#define		HPD2_INT				BIT(17)
#define		HPD2_RX_INT				BIT(18)
#define DISP3_INT_STATUS			0x6100
#define		LB_D3_VLINE_INT				BIT(2)
#define		LB_D3_VBLANK_INT			BIT(3)
#define		HPD3_INT				BIT(17)
#define		HPD3_RX_INT				BIT(18)
#define DISP4_INT_STATUS			0x614c
#define		LB_D4_VLINE_INT				BIT(2)
#define		LB_D4_VBLANK_INT			BIT(3)
#define		HPD4_INT				BIT(17)
#define		HPD4_RX_INT				BIT(18)
#define DISP5_INT_STATUS			0x6150
#define		LB_D5_VLINE_INT				BIT(2)
#define		LB_D5_VBLANK_INT			BIT(3)
#define		HPD5_INT				BIT(17)
#define		HPD5_RX_INT				BIT(18)

#define	DACA_AUTODETECT_INT_CTL			0x66c8
#define	DACB_AUTODETECT_INT_CTL			0x67c8

/*----------------------------------------------------------------------------*/
/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */
#define CRTC0_REG_OF		(0x6df0 - 0x6df0)
#define CRTC1_REG_OF		(0x79f0 - 0x6df0)
/* many regs here */
#define CRTC2_REG_OF		(0x105f0 - 0x6df0)
#define CRTC3_REG_OF		(0x111f0 - 0x6df0)
#define CRTC4_REG_OF		(0x11df0 - 0x6df0)
#define CRTC5_REG_OF		(0x129f0 - 0x6df0)
/*----------------------------------------------------------------------------*/

/* grph blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
#define GRPH_ENA				0x6800
#define GRPH_CTL				0x6804
#define		GRPH_DEPTH_MASK				0x00000003
#define		GRPH_DEPTH_SHIFT			0
#define			GRPH_DEPTH_8BPP				0
#define			GRPH_DEPTH_16BPP			1
#define			GRPH_DEPTH_32BPP			2
#define		GRPH_BANKS_N_MASK			0x0000000c
#define		GRPH_BANKS_N_SHIFT			2
#define			ADDR_SURF_2_BANK			0
#define			ADDR_SURF_4_BANK			1
#define			ADDR_SURF_8_BANK			2
#define			ADDR_SURF_16_BANK			3
#define		GRPH_Z_MASK				0x00000030
#define		GRPH_Z_SHIFT				4
#define		GRPH_BANK_W_MASK			0x000000c0
#define		GRPH_BANK_W_SHIFT			6
#define			ADDR_SURF_BANK_WIDTH_1			0
#define			ADDR_SURF_BANK_WIDTH_2			1
#define			ADDR_SURF_BANK_WIDTH_4			2
#define			ADDR_SURF_BANK_WIDTH_8			3
#define		GRPH_FMT_MASK				0x00000700
#define		GRPH_FMT_SHIFT				8
			/* 8 bpp */
#define			GRPH_FMT_INDEXED			0
			/* 16 bpp */
#define			GRPH_FMT_ARGB1555			0
#define			GRPH_FMT_ARGB565			1
#define			GRPH_FMT_ARGB4444			2
#define			GRPH_FMT_AI88				3
#define			GRPH_FMT_MONO16				4
#define			GRPH_FMT_BGRA5551			5
			/* 32 bpp */
#define			GRPH_FMT_ARGB8888			0
#define			GRPH_FMT_ARGB2101010			1
#define			GRPH_FMT_32BPP_DIG			2
#define			GRPH_FMT_8B_ARGB2101010			3
#define			GRPH_FMT_BGRA1010102			4
#define			GRPH_FMT_8B_BGRA1010102			5
#define			GRPH_FMT_RGB111110			6
#define			GRPH_FMT_BGR101111			7
#define		GRPH_BANK_H_MASK			0x00001800
#define		GRPH_BANK_H_SHIFT			11
#define			ADDR_SURF_BANK_HEIGHT_1			0
#define			ADDR_SURF_BANK_HEIGHT_2			1
#define			ADDR_SURF_BANK_HEIGHT_4			2
#define			ADDR_SURF_BANK_HEIGHT_8			3
#define		GRPH_TILE_SPLIT_MASK			0x0000e000
#define		GRPH_TILE_SPLIT_SHIFT			13
#define			ADDR_SURF_TILE_SPLIT_64B		0
#define			ADDR_SURF_TILE_SPLIT_128B		1
#define			ADDR_SURF_TILE_SPLIT_256B		2
#define			ADDR_SURF_TILE_SPLIT_512B		3
#define			ADDR_SURF_TILE_SPLIT_1KB		4
#define			ADDR_SURF_TILE_SPLIT_2KB		5
#define			ADDR_SURF_TILE_SPLIT_4KB		6
#define		GRPH_MACRO_TILE_ASPECT_MASK		0x000c0000
#define		GRPH_MACRO_TILE_ASPECT_SHIFT		18
#define			ADDR_SURF_MACRO_TILE_ASPECT_1		0
#define			ADDR_SURF_MACRO_TILE_ASPECT_2		1
#define			ADDR_SURF_MACRO_TILE_ASPECT_4		2
#define			ADDR_SURF_MACRO_TILE_ASPECT_8		3
#define		GRPH_ARRAY_MODE_MASK			0x00700000
#define		GRPH_ARRAY_MODE_SHIFT			20
#define			GRPH_ARRAY_LINEAR_GENERAL		0
#define			GRPH_ARRAY_LINEAR_ALIGNED		1
#define			GRPH_ARRAY_1D_TILED_THIN1		2
#define			GRPH_ARRAY_2D_TILED_THIN1		4
#define GRPH_SWAP_CTL				0x680c
#define		GRPH_ENDIAN_SWAP_MASK			0x00000003
#define		GRPH_ENDIAN_SWAP_SHIFT			0
#define			GRPH_ENDIAN_NONE			0
#define			GRPH_ENDIAN_8IN16			1
#define			GRPH_ENDIAN_8IN32			2
#define			GRPH_ENDIAN_8IN64			3
#define		GRPH_RED_CROSSBAR_MASK			0x00000030
#define		GRPH_RED_CROSSBAR_SHIFT			4
#define			GRPH_RED_SEL_R				0
#define			GRPH_RED_SEL_G				1
#define			GRPH_RED_SEL_B				2
#define			GRPH_RED_SEL_A				3
#define		GRPH_GREEN_CROSSBAR_MASK		0x000000c0
#define		GRPH_GREEN_CROSSBAR_SHIFT		6
#define			GRPH_GREEN_SEL_G			0
#define			GRPH_GREEN_SEL_B			1
#define			GRPH_GREEN_SEL_A			2
#define			GRPH_GREEN_SEL_R			3
#define		GRPH_BLUE_CROSSBAR_MASK			0x00000300
#define		GRPH_BLUE_CROSSBAR_SHIFT		8
#define			GRPH_BLUE_SEL_B				0
#define			GRPH_BLUE_SEL_A				1
#define			GRPH_BLUE_SEL_R				2
#define			GRPH_BLUE_SEL_G				3
#define		GRPH_ALPHA_CROSSBAR_MASK		0x00000c00
#define		GRPH_ALPHA_CROSSBAR_SHIFT		10
#define			GRPH_ALPHA_SEL_A			0
#define			GRPH_ALPHA_SEL_R			1
#define			GRPH_ALPHA_SEL_G			2
#define			GRPH_ALPHA_SEL_B			3
#define GRPH_PRIMARY_SURF_ADDR			0x6810
#define GRPH_SECONDARY_SURF_ADDR		0x6814
#define		GRPH_DFQ_ENA				BIT(0)
#define		GRPH_SURF_ADDR_MASK			0xffffff00
#define GRPH_PITCH				0x6818
#define GRPH_PRIMARY_SURF_ADDR_HIGH		0x681c
#define GRPH_SECONDARY_SURF_ADDR_HIGH		0x6820
#define GRPH_SURF_OF_X				0x6824
#define GRPH_SURF_OF_Y				0x6828
#define GRPH_X_START				0x682c
#define GRPH_Y_START				0x6830
#define GRPH_X_END				0x6834
#define GRPH_Y_END				0x6838
#define GRPH_UPDATE				0x6844
#define		GRPH_SURF_UPDATE_PENDING		BIT(2)
#define		GRPH_UPDATE_LOCK			BIT(16)
#define GRPH_FLIP_CTL				0x6848
#define		GRPH_SURF_UPDATE_H_RETRACE_ENA		BIT(0)

/* 0x6858 ... */
#define GRPH_INT_STATUS				0x6858
#define		GRPH_PFLIP_INT_OCCURRED			BIT(0)
#define		GRPH_PFLIP_INT_CLR			BIT(8)

/* 0x685c ... */
#define	GRPH_INT_CTL				0x685c
#define		GRPH_PFLIP_INT_MASK			BIT(0)
#define		GRPH_PFLIP_INT_TYPE			BIT(8)

/* 0x69e0 ... */
#define LUT_RW_MODE				0x69e0
#define LUT_RW_IDX				0x69e4
#define LUT_30_COLOR				0x69f0
#define LUT_WR_ENA_MASK				0x69f8
#define LUT_CTL					0x6a00
#define LUT_BLACK_OF_BLUE			0x6a04
#define LUT_BLACK_OF_GREEN			0x6a08
#define LUT_BLACK_OF_RED			0x6a0c
#define LUT_WHITE_OF_BLUE			0x6a10
#define LUT_WHITE_OF_GREEN			0x6a14
#define LUT_WHITE_OF_RED			0x6a18

/* 0x6b04 ... */
#define DESKTOP_HEIGHT				0x6b04
#define VLINE_START_END				0x6b08

/* 0x6b40 ... */
#define INT_MASK				0x6b40
#define		VBLANK_INT_MASK				BIT(0)
#define		VLINE_INT_MASK				BIT(4)

/* 0x6bb8 ... */
#define VLINE_STATUS				0x6bb8
#define		VLINE_OCCURRED				BIT(0)
#define		VLINE_ACK				BIT(4)
#define		VLINE_STAT				BIT(12)
#define		VLINE_INT				BIT(16)
#define		VLINE_INT_TYPE				BIT(17)

/* 0x6bbc ... */
#define VBLANK_STATUS				0x6bbc
#define		VBLANK_OCCURRED				BIT(0)
#define		VBLANK_ACK				BIT(4)
#define		VBLANK_STAT				BIT(12)
#define		VBLANK_INT				BIT(16)
#define		VBLANK_INT_TYPE				BIT(17)

#define VIEWPORT_START				0x6d70
#define VIEWPORT_SZ				0x6d74

/* 0x6e70 ... */
#define CRTC_CTL				0x6e70
#define		CRTC_MASTER_ENA				BIT(0)
#define		CRTC_DISP_READ_REQ_DIS			BIT(24)
#define CRTC_STATUS_FRAME_CNT			0x6e98
#define CRTC_UPDATE_LOCK			0x6ed4
#define MASTER_UPDATE_MODE			0x6ef8

static u32 regs_lut_30_color[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_30_COLOR + CRTC0_REG_OF,
	LUT_30_COLOR + CRTC1_REG_OF,
	LUT_30_COLOR + CRTC2_REG_OF,
	LUT_30_COLOR + CRTC3_REG_OF,
	LUT_30_COLOR + CRTC4_REG_OF,
	LUT_30_COLOR + CRTC5_REG_OF
};

static u32 regs_lut_rw_idx[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_RW_IDX + CRTC0_REG_OF,
	LUT_RW_IDX + CRTC1_REG_OF,
	LUT_RW_IDX + CRTC2_REG_OF,
	LUT_RW_IDX + CRTC3_REG_OF,
	LUT_RW_IDX + CRTC4_REG_OF,
	LUT_RW_IDX + CRTC5_REG_OF
};

static u32 regs_lut_write_ena_mask[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_WR_ENA_MASK + CRTC0_REG_OF,
	LUT_WR_ENA_MASK + CRTC1_REG_OF,
	LUT_WR_ENA_MASK + CRTC2_REG_OF,
	LUT_WR_ENA_MASK + CRTC3_REG_OF,
	LUT_WR_ENA_MASK + CRTC4_REG_OF,
	LUT_WR_ENA_MASK + CRTC5_REG_OF
};

static u32 regs_lut_rw_mode[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_RW_MODE + CRTC0_REG_OF,
	LUT_RW_MODE + CRTC1_REG_OF,
	LUT_RW_MODE + CRTC2_REG_OF,
	LUT_RW_MODE + CRTC3_REG_OF,
	LUT_RW_MODE + CRTC4_REG_OF,
	LUT_RW_MODE + CRTC5_REG_OF
};

static u32 regs_lut_white_of_red[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_WHITE_OF_RED + CRTC0_REG_OF,
	LUT_WHITE_OF_RED + CRTC1_REG_OF,
	LUT_WHITE_OF_RED + CRTC2_REG_OF,
	LUT_WHITE_OF_RED + CRTC3_REG_OF,
	LUT_WHITE_OF_RED + CRTC4_REG_OF,
	LUT_WHITE_OF_RED + CRTC5_REG_OF
};

static u32 regs_lut_white_of_green[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_WHITE_OF_GREEN + CRTC0_REG_OF,
	LUT_WHITE_OF_GREEN + CRTC1_REG_OF,
	LUT_WHITE_OF_GREEN + CRTC2_REG_OF,
	LUT_WHITE_OF_GREEN + CRTC3_REG_OF,
	LUT_WHITE_OF_GREEN + CRTC4_REG_OF,
	LUT_WHITE_OF_GREEN + CRTC5_REG_OF
};

static u32 regs_lut_white_of_blue[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_WHITE_OF_BLUE + CRTC0_REG_OF,
	LUT_WHITE_OF_BLUE + CRTC1_REG_OF,
	LUT_WHITE_OF_BLUE + CRTC2_REG_OF,
	LUT_WHITE_OF_BLUE + CRTC3_REG_OF,
	LUT_WHITE_OF_BLUE + CRTC4_REG_OF,
	LUT_WHITE_OF_BLUE + CRTC5_REG_OF
};

static u32 regs_lut_black_of_red[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_BLACK_OF_RED + CRTC0_REG_OF,
	LUT_BLACK_OF_RED + CRTC1_REG_OF,
	LUT_BLACK_OF_RED + CRTC2_REG_OF,
	LUT_BLACK_OF_RED + CRTC3_REG_OF,
	LUT_BLACK_OF_RED + CRTC4_REG_OF,
	LUT_BLACK_OF_RED + CRTC5_REG_OF
};

static u32 regs_lut_black_of_green[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_BLACK_OF_GREEN + CRTC0_REG_OF,
	LUT_BLACK_OF_GREEN + CRTC1_REG_OF,
	LUT_BLACK_OF_GREEN + CRTC2_REG_OF,
	LUT_BLACK_OF_GREEN + CRTC3_REG_OF,
	LUT_BLACK_OF_GREEN + CRTC4_REG_OF,
	LUT_BLACK_OF_GREEN + CRTC5_REG_OF
};

static u32 regs_lut_black_of_blue[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_BLACK_OF_BLUE + CRTC0_REG_OF,
	LUT_BLACK_OF_BLUE + CRTC1_REG_OF,
	LUT_BLACK_OF_BLUE + CRTC2_REG_OF,
	LUT_BLACK_OF_BLUE + CRTC3_REG_OF,
	LUT_BLACK_OF_BLUE + CRTC4_REG_OF,
	LUT_BLACK_OF_BLUE + CRTC5_REG_OF
};

static u32 regs_lut_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LUT_CTL + CRTC0_REG_OF,
	LUT_CTL + CRTC1_REG_OF,
	LUT_CTL + CRTC2_REG_OF,
	LUT_CTL + CRTC3_REG_OF,
	LUT_CTL + CRTC4_REG_OF,
	LUT_CTL + CRTC5_REG_OF
};

static u32 regs_master_update_mode[CRTCS_N_MAX] __attribute__ ((unused)) = {
	MASTER_UPDATE_MODE + CRTC0_REG_OF,
	MASTER_UPDATE_MODE + CRTC1_REG_OF,
	MASTER_UPDATE_MODE + CRTC2_REG_OF,
	MASTER_UPDATE_MODE + CRTC3_REG_OF,
	MASTER_UPDATE_MODE + CRTC4_REG_OF,
	MASTER_UPDATE_MODE + CRTC5_REG_OF
};

static u32 regs_grph_flip_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_FLIP_CTL + CRTC0_REG_OF,
	GRPH_FLIP_CTL + CRTC1_REG_OF,
	GRPH_FLIP_CTL + CRTC2_REG_OF,
	GRPH_FLIP_CTL + CRTC3_REG_OF,
	GRPH_FLIP_CTL + CRTC4_REG_OF,
	GRPH_FLIP_CTL + CRTC5_REG_OF
};

static u32 regs_viewport_sz[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VIEWPORT_SZ + CRTC0_REG_OF,
	VIEWPORT_SZ + CRTC1_REG_OF,
	VIEWPORT_SZ + CRTC2_REG_OF,
	VIEWPORT_SZ + CRTC3_REG_OF,
	VIEWPORT_SZ + CRTC4_REG_OF,
	VIEWPORT_SZ + CRTC5_REG_OF
};

static u32 regs_viewport_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VIEWPORT_START + CRTC0_REG_OF,
	VIEWPORT_START + CRTC1_REG_OF,
	VIEWPORT_START + CRTC2_REG_OF,
	VIEWPORT_START + CRTC3_REG_OF,
	VIEWPORT_START + CRTC4_REG_OF,
	VIEWPORT_START + CRTC5_REG_OF
};

static u32 regs_desktop_height[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DESKTOP_HEIGHT + CRTC0_REG_OF,
	DESKTOP_HEIGHT + CRTC1_REG_OF,
	DESKTOP_HEIGHT + CRTC2_REG_OF,
	DESKTOP_HEIGHT + CRTC3_REG_OF,
	DESKTOP_HEIGHT + CRTC4_REG_OF,
	DESKTOP_HEIGHT + CRTC5_REG_OF
};

static u32 regs_grph_ena[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_ENA + CRTC0_REG_OF,
	GRPH_ENA + CRTC1_REG_OF,
	GRPH_ENA + CRTC2_REG_OF,
	GRPH_ENA + CRTC3_REG_OF,
	GRPH_ENA + CRTC4_REG_OF,
	GRPH_ENA + CRTC5_REG_OF
};

static u32 regs_grph_pitch[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_PITCH + CRTC0_REG_OF,
	GRPH_PITCH + CRTC1_REG_OF,
	GRPH_PITCH + CRTC2_REG_OF,
	GRPH_PITCH + CRTC3_REG_OF,
	GRPH_PITCH + CRTC4_REG_OF,
	GRPH_PITCH + CRTC5_REG_OF
};

static u32 regs_grph_y_end[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_Y_END + CRTC0_REG_OF,
	GRPH_Y_END + CRTC1_REG_OF,
	GRPH_Y_END + CRTC2_REG_OF,
	GRPH_Y_END + CRTC3_REG_OF,
	GRPH_Y_END + CRTC4_REG_OF,
	GRPH_Y_END + CRTC5_REG_OF
};

static u32 regs_grph_x_end[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_X_END + CRTC0_REG_OF,
	GRPH_X_END + CRTC1_REG_OF,
	GRPH_X_END + CRTC2_REG_OF,
	GRPH_X_END + CRTC3_REG_OF,
	GRPH_X_END + CRTC4_REG_OF,
	GRPH_X_END + CRTC5_REG_OF
};

static u32 regs_grph_y_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_Y_START + CRTC0_REG_OF,
	GRPH_Y_START + CRTC1_REG_OF,
	GRPH_Y_START + CRTC2_REG_OF,
	GRPH_Y_START + CRTC3_REG_OF,
	GRPH_Y_START + CRTC4_REG_OF,
	GRPH_Y_START + CRTC5_REG_OF
};

static u32 regs_grph_x_start[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_X_START + CRTC0_REG_OF,
	GRPH_X_START + CRTC1_REG_OF,
	GRPH_X_START + CRTC2_REG_OF,
	GRPH_X_START + CRTC3_REG_OF,
	GRPH_X_START + CRTC4_REG_OF,
	GRPH_X_START + CRTC5_REG_OF
};

static u32 regs_grph_surf_of_y[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_SURF_OF_Y + CRTC0_REG_OF,
	GRPH_SURF_OF_Y + CRTC1_REG_OF,
	GRPH_SURF_OF_Y + CRTC2_REG_OF,
	GRPH_SURF_OF_Y + CRTC3_REG_OF,
	GRPH_SURF_OF_Y + CRTC4_REG_OF,
	GRPH_SURF_OF_Y + CRTC5_REG_OF
};

static u32 regs_grph_surf_of_x[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_SURF_OF_X + CRTC0_REG_OF,
	GRPH_SURF_OF_X + CRTC1_REG_OF,
	GRPH_SURF_OF_X + CRTC2_REG_OF,
	GRPH_SURF_OF_X + CRTC3_REG_OF,
	GRPH_SURF_OF_X + CRTC4_REG_OF,
	GRPH_SURF_OF_X + CRTC5_REG_OF
};

static u32 regs_grph_swap_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_SWAP_CTL + CRTC0_REG_OF,
	GRPH_SWAP_CTL + CRTC1_REG_OF,
	GRPH_SWAP_CTL + CRTC2_REG_OF,
	GRPH_SWAP_CTL + CRTC3_REG_OF,
	GRPH_SWAP_CTL + CRTC4_REG_OF,
	GRPH_SWAP_CTL + CRTC5_REG_OF
};

static u32 regs_grph_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_CTL + CRTC0_REG_OF,
	GRPH_CTL + CRTC1_REG_OF,
	GRPH_CTL + CRTC2_REG_OF,
	GRPH_CTL + CRTC3_REG_OF,
	GRPH_CTL + CRTC4_REG_OF,
	GRPH_CTL + CRTC5_REG_OF
};

static u32 regs_grph_update[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_UPDATE + CRTC0_REG_OF,
	GRPH_UPDATE + CRTC1_REG_OF,
	GRPH_UPDATE + CRTC2_REG_OF,
	GRPH_UPDATE + CRTC3_REG_OF,
	GRPH_UPDATE + CRTC4_REG_OF,
	GRPH_UPDATE + CRTC5_REG_OF
};

static u32 regs_crtc_status_frame_cnt[CRTCS_N_MAX]
						__attribute__ ((unused)) = {
	CRTC_STATUS_FRAME_CNT + CRTC0_REG_OF,
	CRTC_STATUS_FRAME_CNT + CRTC1_REG_OF,
	CRTC_STATUS_FRAME_CNT + CRTC2_REG_OF,
	CRTC_STATUS_FRAME_CNT + CRTC3_REG_OF,
	CRTC_STATUS_FRAME_CNT + CRTC4_REG_OF,
	CRTC_STATUS_FRAME_CNT + CRTC5_REG_OF
};

static u32 regs_crtc_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	CRTC_CTL + CRTC0_REG_OF,
	CRTC_CTL + CRTC1_REG_OF,
	CRTC_CTL + CRTC2_REG_OF,
	CRTC_CTL + CRTC3_REG_OF,
	CRTC_CTL + CRTC4_REG_OF,
	CRTC_CTL + CRTC5_REG_OF
};

static u32 regs_grph_primary_surf_addr_high[CRTCS_N_MAX]
						__attribute__ ((unused)) = {
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC0_REG_OF,
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC1_REG_OF,
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC2_REG_OF,
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC3_REG_OF,
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC4_REG_OF,
	GRPH_PRIMARY_SURF_ADDR_HIGH + CRTC5_REG_OF
};

static u32 regs_grph_secondary_surf_addr_high[CRTCS_N_MAX]
						__attribute__ ((unused)) = {
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC0_REG_OF,
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC1_REG_OF,
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC2_REG_OF,
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC3_REG_OF,
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC4_REG_OF,
	GRPH_SECONDARY_SURF_ADDR_HIGH + CRTC5_REG_OF
};

static u32 regs_grph_primary_surf_addr[CRTCS_N_MAX]
						__attribute__ ((unused)) = {
	GRPH_PRIMARY_SURF_ADDR + CRTC0_REG_OF,
	GRPH_PRIMARY_SURF_ADDR + CRTC1_REG_OF,
	GRPH_PRIMARY_SURF_ADDR + CRTC2_REG_OF,
	GRPH_PRIMARY_SURF_ADDR + CRTC3_REG_OF,
	GRPH_PRIMARY_SURF_ADDR + CRTC4_REG_OF,
	GRPH_PRIMARY_SURF_ADDR + CRTC5_REG_OF
};

static u32 regs_grph_secondary_surf_addr[CRTCS_N_MAX]
						__attribute__ ((unused)) = {
	GRPH_SECONDARY_SURF_ADDR + CRTC0_REG_OF,
	GRPH_SECONDARY_SURF_ADDR + CRTC1_REG_OF,
	GRPH_SECONDARY_SURF_ADDR + CRTC2_REG_OF,
	GRPH_SECONDARY_SURF_ADDR + CRTC3_REG_OF,
	GRPH_SECONDARY_SURF_ADDR + CRTC4_REG_OF,
	GRPH_SECONDARY_SURF_ADDR + CRTC5_REG_OF
};

static u32 regs_hpd_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	HPD0_INT_STATUS,
	HPD1_INT_STATUS,
	HPD2_INT_STATUS,
	HPD3_INT_STATUS,
	HPD4_INT_STATUS,
	HPD5_INT_STATUS
};

static u32 regs_hpd_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	HPD0_INT_CTL,
	HPD1_INT_CTL,
	HPD2_INT_CTL,
	HPD3_INT_CTL,
	HPD4_INT_CTL,
	HPD5_INT_CTL
};

static u32 regs_hpd_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	HPD0_CTL,
	HPD1_CTL,
	HPD2_CTL,
	HPD3_CTL,
	HPD4_CTL,
	HPD5_CTL
};

static u32 regs_crtc_int_mask[CRTCS_N_MAX] __attribute__ ((unused)) = {
	INT_MASK + CRTC0_REG_OF,
	INT_MASK + CRTC1_REG_OF,
	INT_MASK + CRTC2_REG_OF,
	INT_MASK + CRTC3_REG_OF,
	INT_MASK + CRTC4_REG_OF,
	INT_MASK + CRTC5_REG_OF
};

static u32 regs_crtc_grph_int_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_INT_CTL + CRTC0_REG_OF,
	GRPH_INT_CTL + CRTC1_REG_OF,
	GRPH_INT_CTL + CRTC2_REG_OF,
	GRPH_INT_CTL + CRTC3_REG_OF,
	GRPH_INT_CTL + CRTC4_REG_OF,
	GRPH_INT_CTL + CRTC5_REG_OF
};

static u32 regs_disp_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	DISP0_INT_STATUS,
	DISP1_INT_STATUS,
	DISP2_INT_STATUS,
	DISP3_INT_STATUS,
	DISP4_INT_STATUS,
	DISP5_INT_STATUS
};

static u32 regs_crtc_grph_int_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	GRPH_INT_STATUS + CRTC0_REG_OF,
	GRPH_INT_STATUS + CRTC1_REG_OF,
	GRPH_INT_STATUS + CRTC2_REG_OF,
	GRPH_INT_STATUS + CRTC3_REG_OF,
	GRPH_INT_STATUS + CRTC4_REG_OF,
	GRPH_INT_STATUS + CRTC5_REG_OF
};

static u32 regs_crtc_vblank_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VBLANK_STATUS + CRTC0_REG_OF,
	VBLANK_STATUS + CRTC1_REG_OF,
	VBLANK_STATUS + CRTC2_REG_OF,
	VBLANK_STATUS + CRTC3_REG_OF,
	VBLANK_STATUS + CRTC4_REG_OF,
	VBLANK_STATUS + CRTC5_REG_OF
};

static u32 regs_crtc_vline_status[CRTCS_N_MAX] __attribute__ ((unused)) = {
	VLINE_STATUS + CRTC0_REG_OF,
	VLINE_STATUS + CRTC1_REG_OF,
	VLINE_STATUS + CRTC2_REG_OF,
	VLINE_STATUS + CRTC3_REG_OF,
	VLINE_STATUS + CRTC4_REG_OF,
	VLINE_STATUS + CRTC5_REG_OF
};

static u32 regs_crtc_update_lock[CRTCS_N_MAX] __attribute__ ((unused)) = {
	CRTC_UPDATE_LOCK + CRTC0_REG_OF,
	CRTC_UPDATE_LOCK + CRTC1_REG_OF,
	CRTC_UPDATE_LOCK + CRTC2_REG_OF,
	CRTC_UPDATE_LOCK + CRTC3_REG_OF,
	CRTC_UPDATE_LOCK + CRTC4_REG_OF,
	CRTC_UPDATE_LOCK + CRTC5_REG_OF
};

static u32 vals_hpd_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	HPD0_INT,
	HPD1_INT,
	HPD2_INT,
	HPD3_INT,
	HPD4_INT,
	HPD5_INT
};

static u32 vals_lb_d_vblank_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LB_D0_VBLANK_INT,
	LB_D1_VBLANK_INT,
	LB_D2_VBLANK_INT,
	LB_D3_VBLANK_INT,
	LB_D4_VBLANK_INT,
	LB_D5_VBLANK_INT
};

static u32 vals_lb_d_vline_int[CRTCS_N_MAX] __attribute__ ((unused)) = {
	LB_D0_VLINE_INT,
	LB_D1_VLINE_INT,
	LB_D2_VLINE_INT,
	LB_D3_VLINE_INT,
	LB_D4_VLINE_INT,
	LB_D5_VLINE_INT
};

static u32 regs_vga_ctl[CRTCS_N_MAX] __attribute__ ((unused)) = {
	D0VGA_CTL,
	D1VGA_CTL,
	D2VGA_CTL,
	D3VGA_CTL,
	D4VGA_CTL,
	D5VGA_CTL
};
#endif
